This invention relates to peripheral bus bridges, and more particularly to concurrent transactions on a multi-port PCI bridge.
The rapid and widespread acceptance of the personal computer (PC) is in part due to the ability to expand its functionality. Expansion cards could be inserted into AT-bus connectors in early PC""s, allowing a modem, network adapter, expansion memory, or audio card to be added to the PC. While many PC""s continue to use the AT expansion bus, many also include the higher-performance Peripheral Component Interconnect (PCI) bus. Higher-performance PCI cards can be inserted into PCI connectors or slots on such PC""s.
Various chip sets have been developed to interface the PC""s local processor bus to one or more PCI buses. The PCI bus can be divided or segmented into two or more PCI buses, thus reducing the bus loading and improving performance. Various PCI-to-PCI bus bridges have been developed. While many 2-port bridges are available, a multi-port bridge allows 3 or more PCI busses to be used, further dividing the bus load and potentially improving performance. Compare Olarig, U.S. Pat. No. 5,878,237 to Lange, U.S. Pat. No. 5,941,970.
While PCI bridges are useful, it is desirable for the bridge to be able to handle concurrent transactions from different buses. While some concurrency is permitted, transaction concurrency may be limited to memory transactions for different addresses, such as for different lines in a cache.
What is desired is a multi-port PCI-to-PCI bridge. A PCI bridge that can connect to more than two PCI buses is desirable. A multi-port PCI bridge that processes concurrent transactions is desired. Concurrent transaction processing without memory address limitations is further desired.